In today's world of portable electronic device computing, digital communication and large server farms, ever-increasing computing speed and decreased power consumption are actively pursued. Complex computing applications, sophisticated communication algorithms, and large server access loading drive the demand for computing speed. User demand for increased time between battery recharge cycles and the large energy requirements of server farms drive the pursuit of decreased power consumption. Advancing the state of the art in computing speed while reducing power consumption is difficult because the two issues are directly related. In general, increasing the clock speed of a given hardware configuration results in higher power consumption.
A primary data bandwidth bottleneck and power consumption portion of current computing devices are the memory channel and other parallel buses used to access addressable devices. Such channels and buses (e.g., communication channels associated with current-art memory technologies such as double data rate (“DDR”) synchronous dynamic random-access memory (“SDRAM”)) consume a significant amount of power in the termination load associated with each address, control, and clock signal path. The latter termination loads often consist of one or more fixed termination resistors electrically connected at the receiver end of each bus signal path. The termination resistors load the bus at the receiver end to absorb high-speed bus signals that might otherwise be reflected back to receiving devices on the bus. Such reflections can interfere with the coherent reception of the bus signals at the receiving devices.
FIG. 1 is a prior-art schematic diagram of a computer memory bus 105. The computer memory bus 105 is an example of a parallel digital signal bus to which embodiments described herein are applicable. In the case of the example memory bus 105, address and control (“ADD/CTRL”) signals are imposed on bus conductors 110 by a memory controller 115. The memory controller 115 also transmits one or more clock signals on bus conductors 120. The clock signals are used to clock address and control words into dynamic random access (“DRAM”) devices 125. Addressed data words are transmitted to or retrieved from the DRAM devices 125 on a data (“DQ”) bus 130.
Address, control and clock bus conductors are typically each individually terminated at the end 135 of the bus 105 that is furthest from the memory controller 115, at a point past the last bus device (e.g., the DRAM device 140). The end 135 of the bus 105 is referred to herein as the “receiver end” of the bus. Each of the bus conductors 110, 120 is typically terminated with a fixed-value resistor R_TERM (e.g., the resistor R_TERM 145). Each termination resistor R_TERM is connected between the receiver end of the corresponding bus conductor and a common regulated voltage node 150 referred to as the “voltage termination terminal” (“VTT”). The voltage level at the regulated voltage node 150 is maintained by a voltage regulator referred to as the “VTT generator” 160.
The described bus termination provides damping for each of the bus conductors 110, 120 to reduce bus signal reflections from the receiver ends 135 of the bus conductors as previously described. A lower resistance value of a termination resistor associated with a particular bus conductor provides greater damping as may be required for higher bus clocking frequencies. However, a lower resistance value also increases current flow through that bus conductor and overall power consumption, even when no signals are being transmitted on the bus conductor. Termination resistance values are thus typically chosen as compromises between power consumption and reliable bus operation at highest anticipated bus clocking rates.